Hardware/Software (HW/SW) co-designed processors often rely on hardware atomic region support to achieve high performance through software dynamic binary optimization. An atomic region generally refers to a region of binary code or computer instructions intended to be completed in sequence without interruption. In dynamic binary optimization, binary codes can be executed in an atomic region and optimized aggressively without considering corner cases such as memory order violation, exception, memory aliasing, etc. If a corner case actually occurs during a transaction, hardware may detect the case and the transaction may be aborted. In this case, an initial state of registers updated or modified by the transaction is restored. Often, this is referred to as rollback.
In order to prepare for possible rollback, hardware often makes a copy or “checkpoint” of registers at entry of the atomic region execution. For example, various HW/SW co-designed processors have implemented an approach utilizing a shadow register file such that at entry of the atomic region execution, an entire register file, e.g., architecture register file, is copied to an entire shadow register file. The data in the shadow register file can be discarded if the atomic region executes and commits successfully. In case of a rollback, the whole shadow register file will be copied back to the whole architecture register file. However, according to the above method, during overlapped atomic region execution, two sets of shadow register files would be needed, effectively doubling the die area and thus the materials and expense associated therewith.